1. Field of the Invention
This invention includes a metal-clad laminate product that may be associated with a substrate wherein the metal-clad laminate product includes a semi-transparent metal layer that is thin enough to allow actinic light to penetrate the semi-transparent metal layer and reach into a photo dielectric layer below. This invention also includes a method for manufacturing circuit board having interlayer vias using metal clad laminates including a semi-transparent metal layer.
2. Description of the Related Art
The electronics industry continues to seek enhanced product performance in order to meet consumer demands for higher functionality and lower cost computers and electronics equipment. Among the methods that the electronic industry is using to increase performance is by the design of circuit boards that have smaller, finer circuit lines and spaces. Increasing line density leads to fewer circuit layers resulting in smaller electronic devices. In addition, the industry is also migrating towards built-up technologies using micro-vias. Multi layer circuit boards using dielectric circuit layers connected by very small holes (vias) significantly densify the circuit due to reduced board area per hole.
Current circuit board designs require substrate materials on which extremely fine lines and spaces can be formed with a high degree of precision. Metal foils are generally a preferred substrate for the formation of circuit lines on circuit boards. The metal films are most commonly formed by electrodeposition. Electrodeposited copper films typically must be of a defined minimum thickness, &gt;1 .mu.m, to avoid holes or discontinuities. Metal foils that are currently in use in the industry are typically at least 5 .mu.ms in thickness. The use of thinner metal foil in printed circuit board would allow the formation of more densely packed lines and would reduce production costs. Thus, there is a significant interest in developing methods for obtaining thin copper foils. Existing methods for obtaining and placing a very thin metal foil on a laminate are limited. One example of methods for using thin metal layer articles of manufacture to prepare printed circuit board layers is disclosed in U.S. patent application Ser. No. 09/075,732, which is incorporated herein by reference.
Photovia processes, which use photoimageable dielectric materials to fabricate builtup multilayer printed circuit boards, have been developed. In these processes, photo dielectrics are coated on a patterned core and photoimaged to define via holes. The via holes along with the surface of the dielectric layer are then plated with copper. U.S. Pat. No. 5,354,593 sequentially laminates and photoimages two photo dielectrics onto a conductive core to define via holes and then copper plates the via holes. U.S. Pat. No. 5,451,721 produces a multilayer printed circuit board by applying a photosensitive resin layer onto a core having a metal line on its surface. After imaging to form vias, the resin layer is deposited with a copper layer by electroless plating techniques. U.S. Pat. No. 5,334,487 produces a patterned layer on a substrate by applying and exposing different photosensitive compositions on opposite sides of a copper foil. One side is developed and the copper etched, followed by developing the other side and metallization of through holes. U.S. Pat. Nos. 5,354,593, 5451,721 and 5,334,487 are each incorporated herein by reference.
Current high density built-up technologies largely depend on via holes and dielectric layers metallized by sputter metal deposition or electroless seeding. Via formation can occur by reactive ion etching, photolithography in the case of photo reactive dielectrics, wet etching, or projection ablation. Photo dielectrics are becoming the most attractive approach due to their fit with current printed wiring board equipment. The subsequent metal layer, being sputtered or electroless deposited, is applied as a seed layer for pattern plating or panel plating circuit formation. Sputter deposition is preferred due to the dry processing, but current printed wiring board infrastructure does not contain sputtering technology, and the technology is limited to small printed wiring boards. Examples of methods and articles of manufacture useful for preparing circuit boards including interlayer vias are disclosed in U.S. patent application Ser. Nos. 09/054,264, and 09/054,263 each of which are incorporated herein by reference. Electroless seeding is possible in many board processes, but the steps require board exposure to severe a pH wet process and give seed layers of poor uniformity, with low conductivity and residual metals trapped within the dielectric after etching. As a result, there is a need for technology that enables via formation with high density circuits that fits many of the current wiring board processes.